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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
Datasheet Version 2.0
The LSISAS1064 is a 4-port, 3.0 Gbit/s SAS/SATA controller that is compliant with the Fusion-MPTTM architecture, provides a PCI-X interface, and supports Integrated RAIDTM. The LSISAS1064 controller brings 3.0 Gbit/s SAS performance to host adapter, workstation, and server designs, making it easy to add a SAS interface to any PCI or PCI-X1 system. The LSISAS1064 integrates four high-performance SAS/SATA phys and a 64-bit, 133 MHz PCI-X bus master DMA core. Each of the four phys on the LSISAS1064 is capable of 3.0 Gbit/s and 1.5 Gbit/s SAS link rates and 3.0 Gbit/s and 1.5 Gbit/s SATA link rates. The LSISAS1064 supports the ANSI Serial Attached SCSI Standard, Version 1.0. The controller also supports the Serial ATA (SATA) protocol defined by the Serial ATA Specification, Version 1.0a. Supporting both the SAS and SATA interfaces, the LSISAS1064 is a versatile controller that provides the backbone of both server and highend workstation environments. Figure 1 shows a direct-connect configuration. Figure 2 provides an example of the LSISAS1064 configured with an LSISASx12 expander. Figure 1 LSISAS1064 Direct-Connect Example Application
Tx , Rx SAS/SATA Device Tx , Rx SAS/SATA Device Tx , Rx SAS/SATA Device Tx , Rx SAS/SATA Device LSISAS1064 64-Bit, 133 MHz PCI-X Controller 32-Bit Memory Address/Data Bus I2C Interface I2C Flash ROM/ PSBRAM/ NVSRAM
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PCI/PCI-X Interface
1. In some instances, this manual references PCI-X explicitly. References to the PCI bus may be inclusive of both the PCI specification and PCI-X addendum, or may only refer to the PCI bus depending on the operating mode of the device.
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Version 2.0
January 2005
Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
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Figure 2
LSISAS1064 Controller and LSISASx12 Expander Example Application
PCI/PCI-X Interface
32-Bit Memory Address/Data Bus
LSISAS1064
Flash ROM/ PSBRAM/ NVSRAM I2C
I2C Interface
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LSISASx12
LSISASx12
SAS/SATA Drives
SAS/SATA Drives
SAS/SATA Drives
SAS/SATA Drives
The SAS interface uses the proven SCSI data transfer command set to ensure reliable data transfers while providing the connectivity and flexibility of point-to-point serial data transfers. The SAS interface provides improved performance, simplified cabling, smaller connectors, lower pin count, and lower power requirements when compared to parallel SCSI. SAS controllers leverage an electrical and physical connection interface that is compatible with Serial ATA technology. Each port on the LSISAS1064 supports SAS and SATA devices using the SAS Serial SCSI Protocol (SSP), Serial Management Protocol (SMP), Serial Tunneling Protocol (STP), and SATA. The SSP enables communication with other SAS devices. SATA enables the LSISAS1064 to communicate with other SATA devices. The SMP communicates topology management information directly with an attached SAS expander device, such as the LSISASx12. STP enables the LSISAS1064 to communicate with a SATA device through an attached expander. The LSISAS1064 supports a 133 MHz, 64-bit PCI-X bus. With the exception that the PCI interface is not tolerant of 5 V PCI, the interface
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
is backward compatible with all revisions of the PCI/PCI-X bus. The LSISAS1064 supports PCI-X split completion cycles and 32-bit or 64-bit data bursts with variable burst length. The LSISAS1064 supports the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0, and the PCI Local Buss Specification, Revision 3.0. The LSISAS1064 supports the Integrated RAID solution, which is a highly integrated, low-cost RAID implementation. It is designed for systems requiring redundancy and high availability but not needing a fullfeatured RAID implementation. The Integrated RAID solution includes Integrated MirroringTM (IM) technology and Integrated StripingTM (IS) technology. IM provides physical mirroring of up to eight physical drives. IM requires a nonvolatile RAM (NVSRAM) to support write journaling. IS enables data striping across up to eight physical drives. The Integrated RAID solution is OS-independent, easy to install and configure, and does not require a special driver. The runtime operation of the Integrated RAID solution is transparent to the operating system. A single firmware build supports all Integrated RAID capabilities. The LSISAS1064 also provides Zero Channel RAID (ZCR) support. The LSISAS1064 is based on the Fusion-MPT (Message Passing Technology) architecture, which features a performance-based message passing protocol that offloads the host CPU by completely managing all I/Os and minimizes system bus overhead by coalescing interrupts. The Fusion-MPT architecture requires only a thin, easy to develop device driver that is independent of the I/O bus. LSI Logic provides this device driver. To meet its flexibility and data transfer requirements, the LSISAS1064 uses an ARM(R)926 processor. The ARM926 offers data cache and instruction cache, which provide a significant performance increase. LSI Logic manufactures the LSISAS1064 controller using the GflxTM technology.
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
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Features
This section provides a summary of the LSISAS1064 features and benefits.
SAS Features
SAS features include:
* * *
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Provides four fully independent phys Supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers for each phy Supports SSP to enable communication with other SAS devices Supports SMP to communicate topology management information Provides a serial, point-to-point, enterprise-level storage interface Simplifies cabling between devices Provides a scalable interface that supports up to 128 devices through multiple expanders Supports wide ports consisting of two, three, or four phys Supports narrow ports consisting of a single phy Transfers data using SCSI information units
* * * * * * *
SATA and STP Features
SATA and STP features include:
* * * * * * *
Supports SATA data transfers of 3.0 Gbits/s and 1.5 Gbits/s Supports STP data transfers of 3.0 Gbits/s and 1.5 Gbits/s Provides a serial, point-to-point storage interface Simplifies cabling between devices Eliminates the Master-Slave construction used in parallel ATA Allows addressing of multiple SATA targets through an expander Allows multiple initiators to address a single target (in a fail-over configuration) through an expander
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
PCI Performance
PCI features of the LSISAS1064 include:
*
Supports a 133 MHz, 64-bit PCI/PCI-X interface that does the following: - - - - - Operates up to 133 MHz PCI-X Operates at 33 MHz or 66 MHz PCI Supports 32-bit or 64-bit data transfers Supports 32-bit or 64-bit addressing through Dual Address Cycles (DAC) Provides a theoretical 1066 Mbytes/s PCI bandwidth Supports 3.3 V PCI, and is not 5 V PCI tolerant Complies with the PCI Local Bus Specification, Revision 3.0 Complies with the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0 Complies with the PCI Power Management Interface Specification, Revision 1.2 Complies with the PC2001 Specification
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- - - - -
* * * * * * * * *
Provides unequaled performance through the Fusion-MPT architecture Provides high throughput and low CPU utilization to offload the host processor Uses a dedicated ARM926 processor Presents a single electrical load to the PCI bus Reduces Interrupt Service Routine (ISR) overhead with interrupt coalescing Supports Message Signaled Interrupts (MSI) and MSI-X Supports 32-bit or 64-bit data bursts with variable burst lengths Supports the PCI Cache Line Size register Supports the PCI Memory Write and Invalidate, Memory Read Line, and Memory Read Multiple commands
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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* *
Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, and Memory Write Block commands Supports up to 16 PCI-X Split Transaction cycles
Integration
These features make the LSISAS1064 easy to integrate:
*
Supports backward compatibility with previous revisions of the PCI specification, with the exception that the LSISAS1064 does not support 5 V PCI Provides a full 32-bit or 64-bit PCI-X DMA bus master Reduces time-to-market with the Fusion-MPT architecture that provides: - - - - Single driver binary for SAS/SATA, SCSI, and Fibre Channel products One firmware build that supports all Integrated RAID capabilities Thin and easy-to-develop drivers Reduced integration and certification effort
*
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*
Usability
The usability features include:
* * * * *
Simplifies cabling with point-to-point, serial architecture Smaller, thinner cables do not restrict airflow Provides drive spin-up sequencing control Provides up to two LED signals for each phy to indicate link activity and faults Provides an Inter-IC (I2C) interface for enclosure management
Flexibility
These features increase the flexibility of the LSISAS1064:
* *
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Supports a Flash ROM interface, an NVSRAM interface, and a pipelined synchronous burst SRAM (PSBRAM) interface Offers a flexible programming interface to tune I/O performance
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
* * * *
Allows mixed connections to SAS or SATA targets Leverages compatible connectors for SAS and SATA connections Allows grouping of up to four phys to form a wide port Allows programming of the World Wide Name
Reliability
These features enhance the reliability of the LSISAS1064:
* * *
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Uses proven GigaBlaze(R) transceivers Isolates the power and ground of I/O pads and internal chip logic Provides 2 kV ESD protection Provides latch-up protection Has a high proportion of power and ground pins Integrated RAID solution provides Integrated Mirroring technology and Integrated Striping technology Supports ZCR
* * * *
Testability
These features enhance the testability of the LSISAS1064:
* * * *
Offers JTAG boundary scan Provides a UART interface for debugging Offers ARM Multi-ICE(R) for debugging the ARM9 processor Offers I2C port to output debug information
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
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Block Diagram Description
Figure 3 provides the block diagram for the LSISAS1064 controller. The following subsections discuss the block diagram. Figure 3 LSISAS1064 Controller Block Diagram
S. EEPROM
Host Interface
PCI-X 133MHz PCI/PCI-X Interface PCI TimerConfig DMA Arbiter
Quad Port
AHB Bridge Queue Manager SATA Engine
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Primary AHB Bus
AHB Interface SECONDARY
System Interface AHB Interface CONTEXT Transport Module ICE I/F AHB Arbiter Quad Port Context AHB Bus Quad Port DMA Arbiter
IOP (ARM926)
IRQ Controller GPIO/LED TimerConfig XMEM Bus External Memory I2C
Port Layer Connection Management and Switch
SAS Link SAS Phy
SAS Link SAS Phy
SAS Link SAS Phy
SAS Link SAS Phy
I2C
UART UART Context RAM
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Host Interface
The LSISAS1064 interfaces with the host through the host interface module. The host interface module contains the PCI/PCI-X interface, system interface, PCI timer and configuration, DMA arbiter, IOP, I2C, and external memory blocks. PCI/PCI-X Interface The LSISAS1064 provides a PCI-X interface that supports up to a 64-bit, 133 MHz PCI-X bus. With the exception that the PCI interface is not tolerant of 5 V PCI, the interface is backward compatible with all previous implementations of the PCI specification.
www..comInterface System
In combination with the IOP, the system interface supports the Fusion-MPT architecture. The system interface efficiently passes messages between the LSISAS1064 and the host interface using a highperformance, packetized mailbox architecture. The LSISAS1064 system interface coalesces PCI interrupts to minimize traffic on the PCI bus and maximize system performance. IOP The LSISAS1064 I/O processor controls the system interface and manages the host side of the Fusion-MPT architecture without host processor intervention, which frees the host processor for other tasks. Timer and Configuration This block supports the LSISAS1064 LED and GPIO interfaces. The GPIO interface contains four independent GPIO signals. This block also supports internal timing adjustments and power-on sense configuration options. DMA Arbiter The LSISAS1064 provides the ability to transfer system memory blocks to and from local memory through the descriptor-based DMA arbiter and router. The DMA channel includes PCI bus master interface logic, a system DMA FIFO, and the internal bus interface logic.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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PCI Timer and Configuration This PCI timer and configuration module supports the PCI configuration register space, an industry-standard, 2-wire serial EEPROM interface, and a power-on reset (POR). A serial EEPROM is not required for typical system configurations. External Memory The external memory controller block provides an interface for Flash ROM, NVSRAM, and PSBRAM devices. The external memory bus provides a 32-bit memory bus, parity checking, and chip select signals for PSBRAM, NVSRAM, and Flash ROM. The Flash ROM and NVSRAM are capable of 8-bit accesses, while the PSBRAM is capable of 32-bit accesses. Typical system configurations require a Flash ROM to store firmware, configuration information, and persistent data information. Inter-IC (I2C) The LSISAS1064 contains an I2C that communicates with peripherals, such as an enclosure management processor. This interface is also referred to as the Industry-Standard 2-Wire Interface (ISTWI). The I2C block operates as either a master or a slave on the bus and sustains data rates up to 400 Kbits/s. The I2C block accomplishes byte-wise bidirectional data transfers by using either an interrupt or a polling handshake at the completion of each byte. The style and operation of this interface closely follows the defacto standard for a two-wire serial interface chip. The I2C block controls all bus timing and performs busspecific sequences. UART The UART provides test and debug access to the LSISAS1064.
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Quad Port
The quad port module in the LSISAS1064 implements the SSP, SMP, and STP/SATA protocols, and manages the four SAS/SATA phys. The following subsections describe the quad port module.
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Transport Module The transport modules transmit frames to and from the port layer and implement the STP, SSP, and SMP protocols. There are four instances of the transport module, one for each SAS/SATA phy on the LSISAS1064. The transport modules also manage DMA transfers. Queue Manager The queue manager is responsible for managing various queue structures that support the SSP, SMP, and SATA/STP protocols. The queue structures are the primary means for the IOP to initiate I/Os to the hardware and for the hardware to notify the IOP of I/O status. SATA Engine www..com The SATA engine provides information to the transport modules to enable handling of SATA commands. The SATA engine tracks queued commands per device and provides these tags to the SATA transport layer blocks. Port Layer Connection Manager and Switch The port layer connection monitor and switch manages transmission requests from the transport modules and originates connection requests to the SAS links. It is also responsible for handling SAS wide port configurations. SAS Link The SAS link layer manages SAS connections between initiator and target ports, data clocking, and CRC checking on transmitted data. The SAS link is also responsible for starting a link reset sequence. SAS Phy The SAS phys interface to the physical layer, perform serial-to-parallel conversion of received data and parallel-to-serial conversion of transmit data, manage phy reset sequences, and perform 8b/10b encoding. Quad Port Arbiter The quad port arbiter interfaces with the host interface DMA arbiter and determines bus priority between each of the four ports for DMA transfers.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
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Context RAM
The context RAM is a memory that is shared between the host interface module and the quad port module. The context RAM holds a portion of the firmware.
Signal Description
The following subsections provide the signal descriptions for the LSISAS1064. A "/" following the signal indicates an active LOW signal.
PCI Signals
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This section describes the PCI signals. Refer to the PCI specification for signal descriptions. PCI System Signals This section describes the PCI system signals. CLK RST/ PCI Address and Data Signals This section describes the PCI address and data signals. AD[63:0] C_BE[7:0]/ PAR PAR64 PCI Interface Control Signals This section describes the PCI interface control signals. GNT/ REQ/ Grant Request Input Output 64-bit Address/Data bus Command/Byte Enable Parity 64-bit Parity Input/Output Input/Output Input/Output Input/Output PCI Clock Reset Input Input
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
REQ64/ ACK64/ IDSEL FRAME/ IRDY/ TRDY/ DEVSEL/ STOP/
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Request 64-bit Acknowledge 64-bit ID Select Frame Initiator Ready Target Ready Device Select Stop Parity Error Error PCI Interrupt A
Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output
PERR/ SERR/ INTA/
PCI-Related Signals
ALT_INTA/ ALT_GNT/ Alternate PCI Interrupt A The alternate interrupt signal is used for ZCR. Output
Read/Write Chip Select Input This active LOW signal provides a chip select during configuration read and write transactions. Enabling ZCR enables this signal. Zero Channel RAID Enable Input This input configures the LSISAS1064 for ZCR operation. Deasserting this signal configures the LSISAS1064 for standard PCI/PCI-X operation. This signal is internally pulled HIGH. Reference Resistance Analog This signal provides the reference resistor node for the PCI-X impedance controller. Reference Resistance Analog This signal provides the reference resistor node for the PCI-X impedance controller.
ZCR_EN/
BZR_SET
BZVDD
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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CompactPCI Signals
This section describes the CompactPCI signals. CPCI_EN/ CompactPCI Enable Input Enabling this active LOW signal configures the LSISAS1064 for the CompactPCI protocol. This signal is internally pulled HIGH. CompactPCI Switch Input This active HIGH signal indicates to the LSISAS1064 device that a change in the system configuration is imminent. This signal is internally pulled LOW.
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CPCI_SWITCH
CPCI_ENUM/ CompactPCI Input/Output This signal informs the system that a board either was freshly inserted or is about to be extracted. This signal remains asserted until the system driver services the hotswapped board. CPCI64_EN/ CompactPCI 64-bit Enable Input This pin indicates the width of the PCI bus when CompactPCI is enabled. Designers must provide a pull-up on this pin when the device is enabled for CompactPCI operation. When CompactPCI is not enabled, designers must leave this pin unconnected. CompactPCI LED Output This active LOW pin provides the CompactPCI Status LED. This is a 3.3 V output.
CPCI_LED/
SAS Signals
This section describes the SAS interface signals. REFCLK_P, REFCLK_N Input These pins provide the serial differential clock. Connect a 75 MHz oscillator with an accuracy of at least 50ppm to these pins. To use a single-ended crystal, tie the crystal to REFCLK_P and tie REFCLK_N to a resistor termination. RTRIM Resistor Reference Analog This pin provides the analog resistor reference for the GigaBlaze transceivers.
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
RX[3:0]-
Receive Negative Differential Data Input RX[x]- provides the negative differential data receiver for phy[x]. Receive Positive Differential Data Input RX[x]+ provides the positive differential data receiver for phy[x]. Transmit Negative Differential Data Output TX[x]- provides the negative differential data transmit signal for phy[x]. Transmit Positive Differential Data Output TX[x]+ provides the positive differential data transmit signal for each phy[x]. Output
RX[3:0]+
TX[3:0]-
TX[3:0]+
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FAULT_LED[3:0]/ Fault LED These output signals indicate a SAS link fault. ACTIVE_LED[3:0]/ Activity LED These output signals indicate SAS link activity.
Output
I2C and Serial EEPROM Signals
This section describes the serial EEPROM and I2C signals. SERIAL_CLK Serial Interface Clock Input/Output This pin provides the serial EEPROM clock signal. SERIAL_DATA Serial Interface Data Input/Output This pin provides the serial EEPROM data signal. ISTW_CLK I2C Clock This pin provides the I2C clock signal. I2C Data This pin provides the I2C data signal. Input/Output
ISTW_DATA
Input/Output
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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Memory Interface Signals
This section describes the memory interface pins. MCLK Memory Clock Output All synchronous RAM control/data signals reference the rising edge of this clock. Address-Strobe-Controller Output Asserting this active LOW signal initiates read, write, or chip deselect cycles. Advance Output Asserting this active LOW signal increments the burst address counter of the selected synchronous SRAM. Multiplexed Address/Data Input/Output These signals provide the address and data bus to the PSBRAM, Flash ROM, and NVSRAM. These signals also provide Power-On Sense configuration functions to the LSISAS1064. These signals are internally pulled LOW. Memory Parity Input/Output These signals provide parity checking for MAD[31:0]. Memory Output Enables Output Asserting these active LOW signals enable the selected PSBRAM, Flash ROM, or NVSRAM device to drive data. MOE[1]/ enables PSBRAM and Flash ROM devices. MOE[0]/ enables NVSRAM devices. MOE[1:0]/ allows interleaved PSBRAM configurations. Memory Write Enables Output The LSISAS1064 uses these active LOW bank write signals for interleaved PSBRAM configurations. Memory Byte Write Enables Output Asserting these active LOW, byte-lane write signals enable partial word writes to the PSBRAM. BWE[3]/ and BWE[2]/ enable partial word writes to the Flash ROM and the NVSRAM if FLASH_CS/ or NVSRAM_CS/ are asserted. NVSRAM Chip Select Output Asserting this active LOW signal selects the NVSRAM device.
ADSC/
ADV/
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MAD[31:0]
MADP[3:0] MOE[1:0]/
MWE[1:0]/
BWE[3:0]/
NVSRAM_CS/
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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PSBRAM_CS/ RAM Chip Select Output Asserting this active LOW signal selects the PSBRAMs. Up to four PSBRAMS are possible in an interleaved and depth-expanded configuration. FLASH_CS/ Flash Chip Select Output Asserting the active LOW signal selects the Flash ROM. The LSISAS1064 maps Flash ROM address space into system memory space.
Configuration and General Purpose Signals
This section describes the configuration and general purpose pins.
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TST_RST/
Test Reset Input Asserting this signal forces the chip into a Power-OnReset state. This signal has an internal pull-up. ARM Reference Clock This pin provides the ARM reference clock. Input
REFCLK_B MODE[5:0]
Mode Select Input This bus defines operational and test modes for the chip. These pins have internal pull-downs. General Purpose I/O Input/Output These pins provide general purpose input/output signals. These pins have internal pull-ups. Heartbeat LED Output Firmware intermittently asserts this signal to indicate that the IOP is operational.
GPIO[3:0]
HB_LED/
JTAG and Test Signals
This section describes the test and JTAG signals. ECC[5:2] FSELA TCK TRST/ ECC These signals are for LSI Logic test purposes only. Clock Select This is a test signal. Pull this signal LOW. JTAG Debug Clock JTAG Debug Reset Input Input Input
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
TDI TDO TMS TCK_ICE RTCK_ICE TRST_ICE/ TDI_ICE TDO_ICE
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JTAG Debug Test Data In JTAG Debug Test Data Out JTAG Debug Test Mode Select Multi-ICE Debug Clock Multi-ICE Debug Return Clock Multi-ICE Debug Reset Multi-ICE Debug Test Data In Multi-ICE Debug Test Data Out Multi-ICE Debug Test Mode Select IDDQ Test Mode Enable 3-State Output Enable Control Process Monitor Test Output Driver
Input Output Input Input Output Input Input Output Input Input Input Output Input/Output Input Output
TMS_ICE IDDTN TN/ PROCMON
TMUXSPARE[7:0] Test Mux Spare TDIODE_P TDIODE_N
Anode Connection of the Thermal Diode Cathode Connection of the Thermal Diode
Power Signals and No Connects
This section describes the power and ground signals. REFPLL_VDD These signals provide 1.2 V power. REFPLL_VSS These signals provide ground. PLL_VDD These signals provide 1.2 V power. PLL_VSS These signals provide ground. VDD2 These signals provide 1.2 V core power. Power Ground Power Ground Power
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LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
VDDIO33 These signals provide 3.3 V I/O power. VDDIO5PCIX VDDIO33PCIX These signals provide 3.3 V PCI I/O power. VSS2 These signals provide ground.
Power Power These signals provide the bias reference for PCI pads. Power Ground
RX_VSS[3:0], RXB_VSS[3:0], TX_VSS[3:0], TXB_VSS[3:0] Ground These signals provide ground for the GigaBlaze core.
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RX_VDD[3:0], RXB_VDD[3:0], TX_VDD[3:0], TXB_VDD[3:0] Power These signals provide 1.2 V power for the GigaBlaze core. NC No Connect No connect signals do not connect to the silicon inside of the LSISAS1064 package. Reserved signals are reserved for LSI Logic use. These signals connect to the LSISAS1064 silicon. Do not connect to Reserved signals.
RESERVED
Pinout
Table 1 provides the signal listing by signal name. Table 2 provides the BGA pin listing. Figure 4 provides a BGA diagram.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
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Table 1
Signal
ACK64/ ACTIVE_LED[0]/ ACTIVE_LED[1]/ ACTIVE_LED[2]/ ACTIVE_LED[3]/ AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] www..com AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] AD[32] AD[33] AD[34] AD[35] AD[36] AD[37] AD[38] AD[39] AD[40] AD[41] AD[42] AD[43] AD[44] AD[45] AD[46] AD[47] AD[48] AD[49] AD[50] AD[51] AD[52] AD[53] AD[54]
Listing by Signal Name
Pin
AE18 H4 G1 H1 L5 AF14 AE17 AD14 AF15 AF13 AF16 AF12 AE11 AF10 AF11 AE9 AB12 AB10 AF9 AD10 AF5 AF4 AE5 AD4 AE4 Y6 Y8 AB3 AE3 Y7 AA5 AA4 AE1 AB2 AC1 V5 AD1 AB24 AC26 AD26 AA23 Y22 W20 AB25 AC25 AC24 Y20 AD24 AF25 AB21 AC20 AA20 AD25 AC23 AA19 AE25 AE24 AF24 AB19 AD22
Signal
AD[55] AD[56] AD[57] AD[58] AD[59] AD[60] AD[61] AD[62] AD[63] ADSC/ ADV/ ALT_GNT/ ALT_INTA/ BWE[0]/ BWE[1]/ BWE[2]/ BWE[3]/ BZR_SET BZVDD C_BE[0]/ C_BE[1]/ C_BE[2]/ C_BE[3]/ C_BE[4]/ C_BE[5]/ C_BE[6]/ C_BE[7]/ CLK CPCI64_EN/ CPCI_LED/ CPCI_EN/ CPCI_ENUM/ CPCI_SWITCH DEVSEL/ ECC2 ECC3 ECC4 ECC5 FAULT_LED[0]/ FAULT_LED[1]/ FAULT_LED[2]/ FAULT_LED[3]/ FLASH_CS/ FRAME/ FSELA GNT/ GPIO[0] GPIO[1] GPIO[2] GPIO[3] HB_LED/ IDDTN IDSEL INTA/ IRDY/ ISTW_CLK ISTW_DATA MAD[0] MAD[1] MAD[2]
Pin
AD23 AF22 AF23 AE22 AE23 AF21 AC19 AF20 AF19 P23 U26 T5 U3 N22 M26 J25 N25 V21 AA24 AE10 AC8 AD6 AD2 AF18 AD19 AF17 AE19 Y4 U2 M5 R1 U1 P1 AD5 Y1 V4 W3 U5 F2 E1 J5 F1 H26 AB7 G5 AA1 J2 K3 L3 K2 J3 N1 AD3 V3 AF6 F22 F21 B26 F23 G23
Signal
MAD[3] MAD[4] MAD[5] MAD[6] MAD[7] MAD[8] MAD[9] MAD[10] MAD[11] MAD[12] MAD[13] MAD[14] MAD[15] MAD[16] MAD[17] MAD[18] MAD[19] MAD[20] MAD[21] MAD[22] MAD[23] MAD[24] MAD[25] MAD[26] MAD[27] MAD[28] MAD[29] MAD[30] MAD[31] MADP[0] MADP[1] MADP[2] MADP[3] MCLK MODE[0] MODE[1] MODE[2] MODE[3] MODE[4] MODE[5] MOE[0]/ MOE[1]/ MWE[0]/ MWE[1]/ N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
Pin
C25 C24 E24 D26 D24 D25 E25 C26 D23 H21 H23 K24 H24 V26 T26 T24 R26 U25 R23 Y26 T22 U24 AA26 V25 V24 W26 R22 AA25 AB26 G21 J26 P26 W23 N26 F3 E2 E3 D1 F4 C2 M22 E26 L26 H25 A11 A16 A21 B8 B22 B23 C8 C14 C15 C19 C20 D6 D7 D8 D9 D14
Signal
N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
Pin
D15 D16 D22 E7 E8 E9 E10 E15 E16 E17 F9 G4 G6 G22 H5 H6 H22 J4 J6 J21 J23 K5 K22 K25 L22 M4 N4 N5 N23 N24 P3 P4 P22 R4 R5 T25 U22 V6 V22 V23 W4 W6 W21 W22 Y5 Y21 AA7 AA8 AA18 AB8 AB9 AB11 AB13 AB15 AB16 AC7 AC9 AC13 AC14 AC15
Note: NC pins are not connected to the LSISAS1064 silicon. RESERVED signals connect to the LSISAS1064 silicon. Do not connect to RESERVED signals.
20 of 30
DB08-000215-04
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Table 1
Signal
N/C N/C N/C N/C N/C NVSRAM_CS/ PAR PAR64 PERR/ PLL_VDD PLL_VSS PROCMON PSBRAM_CS/ REFCLK_B REFCLK_N REFCLK_P REFPLL_VDD REFPLL_VSS REQ/ REQ64/ RESERVED www..com RESERVED RST/ RTCK_ICE RTRIM RXB_VDD0 RXB_VDD1 RXB_VDD2 RXB_VDD3 RXB_VSS0 RXB_VSS1 RXB_VSS2 RXB_VSS3 RX0- RX1- RX2- RX3- RX0+ RX1+ RX2+ RX3+ RX_VDD0 RX_VDD1 RX_VDD2 RX_VDD3 RX_VSS0 RX_VSS1 RX_VSS2 RX_VSS3 SCAN_ENABLE SCAN_MODE SERIAL_CLK SERIAL_DATA SERR/ STOP/ TCK TCK_ICE TDI
Listing by Signal Name (Cont.)
Pin
AC18 AC21 AD11 AE2 AE14 G26 AD9 AB17 AF7 AC4 AC3 M1 J24 D3 J22 F26 D2 C1 AB1 AD18 V2 W2 W5 A5 C9 G19 E19 C17 D12 G20 E20 B18 D13 B25 C21 C16 A14 B24 B21 B16 A13 C23 A22 E14 A12 F20 F18 B17 E12 B2 H7 A8 A7 AF3 AE6 L2 B5 J1
Signal
TDI_ICE TDIODE_P TDIODE_N TDO TDO_ICE TMS TMS_ICE TMUX_SPARE[0] TMUX_SPARE[1] TMUX_SPARE[2] TMUX_SPARE[3] TMUX_SPARE[4] TMUX_SPARE[5] TMUX_SPARE[6] TMUX_SPARE[7] TN/ TRDY/ TRST_ICE/ TRST/ TST_RST/ TXB_VDD0 TXB_VDD1 TXB_VDD2 TXB_VDD3 TXB_VSS0 TXB_VSS1 TXB_VSS2 TXB_VSS3 TX0- TX1- TX2- TX3- TX0+ TX1+ TX2+ TX3+ TX_VDD0 TX_VDD1 TX_VDD2 TX_VDD3 TX_VSS0 TX_VSS1 TX_VSS2 TX_VSS3 UART_RX UART_TX VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDDIO33
Pin
F7 M23 K26 K1 B4 P2 A4 A3 A2 E6 C4 D4 B3 C3 F6 P5 AA9 C5 L1 G7 F19 E18 A18 B10 D21 D19 A17 C10 A23 A19 C13 A9 A24 A20 B13 A10 C22 C18 E13 B9 D20 D18 A15 E11 F8 A6 C11 C12 D10 M13 M15 N12 N14 P13 P15 R12 R14 C6
Signal
VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33 VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO33PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VDDIO5PCIX VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2
Pin
C7 E4 E5 E22 F24 G3 G24 H3 K23 L4 L24 M3 M24 N3 P24 R3 R24 T3 T23 U4 W24 Y3 Y24 AA3 AB5 AB22 AB23 AC5 AC11 AC17 AD7 AD8 AD12 AD13 AD15 AD16 AD20 AD21 V1 W1 Y23 AA6 AA21 AB14 AB18 AB20 AC2 AC6 AC12 AD17 AF8 A25 B1 B6 B7 B11 B12 B14
Signal
VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 ZCR_EN/
Pin
B15 B19 B20 D5 D11 D17 E21 E23 F5 F25 G2 G8 G25 H2 H20 K4 L23 L25 M2 M12 M14 M25 N2 N13 N15 P12 P14 P25 R2 R13 R15 R25 T2 T4 U23 W7 W25 Y2 Y19 Y25 AA2 AA22 AB4 AB6 AC10 AC16 AC22 AE7 AE8 AE12 AE13 AE15 AE16 AE20 AE21 AE26 AF2 T1
Note: NC pins are not connected to the LSISAS1064 silicon. RESERVED signals connect to the LSISAS1064 silicon. Do not connect to RESERVED signals.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
21 of 30
Table 2
Signal
Listing by Pin Number
Pin Signal
C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20
Pin
VDD2 TX2- N/C N/C RX2- RXB_VDD2 TX_VDD1 N/C N/C RX1- TX_VDD0 RX_VDD0 MAD[4] MAD[3] MAD[10] MODE[3] REFPLL_VDD REFCLK_B TMUX_SPARE[4] VSS2 N/C N/C N/C N/C VDD2 VSS2 RXB_VDD3 RXB_VSS3 N/C N/C N/C VSS2 TX_VSS1 TXB_VSS1 TX_VSS0 TXB_VSS0 N/C MAD[11] MAD[7] MAD[8] MAD[6] FAULT_LED[1]/ MODE[1] MODE[2] VDDIO33 VDDIO33 TMUX_SPARE[2] N/C N/C N/C N/C TX_VSS3 RX_VSS3 TX_VDD2 RX_VDD2 N/C N/C N/C TXB_VDD1 RXB_VDD1 RXB_VSS1
Signal
E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H20 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21
Pin
VSS2 VDDIO33 VSS2 MAD[5] MAD[9] MOE[1]/ FAULT_LED[3]/ FAULT_LED[0]/ MODE[0] MODE[4] VSS2 TMUX_SPARE[7] TDI_ICE UART_RX N/C RX_VSS1 TXB_VDD0 RX_VSS0 ISTW_DATA ISTW_CLK MAD[1] VDDIO33 VSS2 REFCLK_P ACTIVE_LED[1]/ VSS2 VDDIO33 N/C FSELA N/C TST_RST/ VSS2 RXB_VDD0 RXB_VSS0 MADP[0] N/C MAD[2] VDDIO33 VSS2 NVSRAM_CS/ ACTIVE_LED[2]/ VSS2 VDDIO33 ACTIVE_LED[0]/ N/C N/C SCAN_MODE VSS2 MAD[12] N/C MAD[13] MAD[15] MWE[1]/ FLASH_CS/ TDI GPIO[0] HB_LED/ N/C FAULT_LED[2]/ N/C N/C
Signal
J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M12 M13 M14 M15 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N12 N13 N14 N15 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P12 P13 P14
Pin
REFCLK_N N/C PSBRAM_CS/ BWE[2]/ MADP[1] TDO GPIO[3] GPIO[1] VSS2 N/C N/C VDDIO33 MAD[14] N/C TDIODE_N TRST/ TCK GPIO[2] VDDIO33 ACTIVE_LED[3]/ N/C VSS2 VDDIO33 VSS2 MWE[0]/ PROCMON VSS2 VDDIO33 N/C CPCI_LED/ VSS2 VDD2 VSS2 VDD2 MOE[0]/ TDIODE_P VDDIO33 VSS2 BWE[1]/ IDDTN VSS2 VDDIO33 N/C N/C VDD2 VSS2 VDD2 VSS2 BWE[0]/ N/C N/C BWE[3]/ MCLK CPCI_SWITCH TMS N/C N/C TN/ VSS2 VDD2 VSS2
A2 TMUX_SPARE[1] A3 TMUX_SPARE[0] A4 TMS_ICE A5 RTCK_ICE A6 UART_TX A7 SERIAL_DATA A8 SERIAL_CLK A9 TX3- A10 TX3+ A11 N/C A12 RX_VDD3 A13 RX3+ A14 RX3- A15 TX_VSS2 A16 N/C A17 TXB_VSS2 A18 TXB_VDD2 A19 TX1- A20 TX1+ A21 N/C A22 www..com RX_VDD1 A23 TX0- A24 TX0+ A25 VSS2 B1 VSS2 B2 SCAN_ENABLE B3 TMUX_SPARE[5] B4 TDO_ICE B5 TCK_ICE B6 VSS2 B7 VSS2 B8 N/C B9 TX_VDD3 B10 TXB_VDD3 B11 VSS2 B12 VSS2 B13 TX2+ B14 VSS2 B15 VSS2 B16 RX2+ B17 RX_VSS2 B18 RXB_VSS2 B19 VSS2 B20 VSS2 B21 RX1+ B22 N/C B23 N/C B24 RX0+ B25 RX0- B26 MAD[0] C1 REFPLL_VSS C2 MODE[5] C3 TMUX_SPARE[6] C4 TMUX_SPARE[3] C5 TRST_ICE/ C6 VDDIO33 C7 VDDIO33 C8 N/C C9 RTRIM C10 TXB_VSS3 C11 VDD2
Note: NC pins are not connected to the LSISAS1064 silicon. RESERVED signals connect to the LSISAS1064 silicon. Do not connect to RESERVED signals.
22 of 30
DB08-000215-04
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Table 2
Signal
Listing by Pin Number (Cont.)
Pin Signal
W6 W7 W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14
Pin
N/C VSS2 AD[37] N/C N/C MADP[3] VDDIO33PCIX VSS2 MAD[28] ECC2 VSS2 VDDIO33PCIX CLK N/C AD[20] AD[24] AD[21] VSS2 AD[41] N/C AD[36] VDDIO5PCIX VDDIO33PCIX VSS2 MAD[22] GNT/ VSS2 VDDIO33PCIX AD[26] AD[25] VDDIO5PCIX N/C N/C TRDY/ N/C AD[49] AD[46] VDDIO5PCIX VSS2 AD[35] BZVDD MAD[30] MAD[25] REQ/ AD[28] AD[22] VSS2 VDDIO33PCIX VSS2 FRAME/ N/C N/C AD[12] N/C AD[11] N/C VDDIO5PCIX
Signal
AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19
Pin
N/C N/C PAR64 VDDIO5PCIX AD[53] VDDIO5PCIX AD[44] VDDIO33PCIX VDDIO33PCIX AD[32] AD[38] MAD[31] AD[29] VDDIO5PCIX PLL_VSS PLL_VDD VDDIO33PCIX VDDIO5PCIX N/C C_BE[1]/ N/C VSS2 VDDIO33PCIX VDDIO5PCIX N/C N/C N/C VSS2 VDDIO33PCIX N/C AD[61] AD[45] N/C VSS2 AD[48] AD[40] AD[39] AD[33] AD[31] C_BE[3]/ IDSEL AD[18] DEVSEL/ C_BE[2]/ VDDIO33PCIX VDDIO33PCIX PAR AD[14] N/C VDDIO33PCIX VDDIO33PCIX AD[2] VDDIO33PCIX VDDIO33PCIX VDDIO5PCIX REQ64/ C_BE[5]/
Signal
AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25
Pin
VDDIO33PCIX VDDIO33PCIX AD[54] AD[55] AD[42] AD[47] AD[34] AD[27] N/C AD[23] AD[19] AD[17] STOP/ VSS2 VSS2 AD[10] C_BE[0]/ AD[7] VSS2 VSS2 N/C VSS2 VSS2 AD[1] ACK64/ C_BE[7]/ VSS2 VSS2 AD[58] AD[59] AD[51] AD[50] VSS2 VSS2 SERR/ AD[16] AD[15] IRDY/ PERR/ VDDIO5PCIX AD[13] AD[8] AD[9] AD[6] AD[4] AD[0] AD[3] AD[5] C_BE[6]/ C_BE[4]/ AD[63] AD[62] AD[60] AD[56] AD[57] AD[52] AD[43]
P15 VDD2 P22 N/C P23 ADSC/ P24 VDDIO33 P25 VSS2 P26 MADP[2] R1 CPCI_EN/ R2 VSS2 R3 VDDIO33 R4 N/C R5 N/C R12 VDD2 R13 VSS2 R14 VDD2 R15 VSS2 R22 MAD[29] R23 MAD[21] R24 VDDIO33 R25 VSS2 R26 MAD[19] T1 ZCR_EN/ www..com T2 VSS2 T3 VDDIO33 T4 VSS2 T5 ALT_GNT/ T22 MAD[23] T23 VDDIO33 T24 MAD[18] T25 N/C T26 MAD[17] U1 CPCI_ENUM/ U2 CPCI64_EN/ U3 ALT_INTA/ U4 VDDIO33 U5 ECC5 U22 N/C U23 VSS2 U24 MAD[24] U25 MAD[20] U26 ADV/ V1 VDDIO5PCIX V2 RESERVED V3 INTA/ V4 ECC3 V5 AD[30] V6 N/C V21 BZR_SET V22 N/C V23 N/C V24 MAD[27] V25 MAD[26] V26 MAD[16] W1 VDDIO5PCIX W2 RESERVED W3 ECC4 W4 N/C W5 RST/
Note: NC pins are not connected to the LSISAS1064 silicon. RESERVED signals connect to the LSISAS1064 silicon. Do not connect to RESERVED signals.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
23 of 30
Figure 4
A2
LSISAS1064 472-Pin BGA Top View
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
TMUX_ SPARE[1]
B1 B2
TMUX_ SPARE[0]
B3
TMS_ICE
B4
RTCK_ICE
B5
UART_TX
B6
SERIAL_ DATA
B7
SERIAL_ CLK
B8 B9
TX3-
B10
TX3+
B11
N/C
RX_VDD3
B12 B13
RX3+
VSS2
C1 C2
SCAN_ ENABLE
TMUX_ SPARE[5]
C3
TDO_ICE
C4
TCK_ICE
C5 C6
VSS2
C7
VSS2
C8
N/C
TX_VDD3
C9
TXB_VDD3
C10 C11
VSS2
C12
VSS2
C13
TX2+
REFPLL_ VSS
D1
MODE[5]
D2
TMUX_ SPARE[6]
D3
TMUX_ SPARE[3]
D4
TRST_ICE
D5
VDDIO33
D6
VDDIO33
D7 D8
N/C
D9
RTRIM
TXB_VSS3
D10 D11
VDD2
D12
VDD2
D13
TX2-
MODE[3]
E1
REFPLL_ VDD
E2
REFCLK_B
E3
TMUX_ SPARE[4]
E4 E5
VSS2
E6
N/C
E7
N/C
E8
N/C
E9
N/C
E10
VDD2
E11
VSS2
RXB_VDD3
E12
RXB_VSS3
E13
FAULT_ LED[1]/
F1 F2
MODE[1]
F3
MODE[2]
VDDIO33
F4
VDDIO33
F5
TMUX_ SPARE[2]
F6 F7
N/C
F8
N/C
F9
N/C
N/C
TX_VSS3
RX_VSS3
TX_VDD2
FAULT_ LED[3]/
G1 G2
FAULT_ LED[0]/
MODE[0]
G3
MODE[4]
G4 G5
VSS2
TMUX_ SPARE[7]
G6
TDI_ICE
G7
UART_RX
G8
N/C
ACTIVE_ LED[1]/
H1 H2
VSS2
VDDIO33
H3 H4
N/C
H5
FSELA
H6
N/C
TST_RST/
H7
VSS2
ACTIVE_ LED[2]/
VSS2
J2 J3
VDDIO33
J4
ACTIVE_ LED[0]/
J5
N/C
J6
N/C
SCAN_ MODE
www..com
TDI
K1 K2
J1
GPIO[0]
HB_LED/
K3 K4
N/C
K5
FAULT_ LED[2]/
N/C
TDO
L1 L2
GPIO[3]
L3
GPIO[1]
L4
VSS2
L5
N/C ACTIVE_ LED[3]/
M5 M12 M13
TRST/
M1 M2
TCK
M3
GPIO[2]
VDDIO33
M4
PROCMON
N1 N2
VSS2
VDDIO33
N3 N4
N/C
CPCI_LED/
N5 N12
VSS2
N13
VDD2
IDDTN
P1 P2
VSS2
VDDIO33
P3 P4
N/C
P5
N/C
P12
VDD2
P13
VSS2
CPCI_ SWITCH
R1 R2
TMS
R3
N/C
R4
N/C
R5
TN/
R12
VSS2
R13
VDD2
CPCI_EN/
T1 T2
VSS2
VDDIO33
T3 T4
N/C
T5
N/C
VDD2
VSS2
ZCR_EN/
U1 U2
VSS2 CPCI64_ EN/
V2
VDDIO33
U3 U4
VSS2
ALT_GNT/
U5
CPCI_ ENUM/
V1
ALT_INTA/
V3
VDDIO33
V4 V5
ECC5
V6
VDDIO5PCIX
W1
RESERVED
W2 W3
INTA/
W4
ECC3
W5
AD[30]
W6
N/C
W7
VDDIO5PCIX
Y1
RESERVED
Y2 Y3
ECC4
Y4
N/C
Y5
RST/
Y6
N/C
Y7
VSS2
Y8
ECC2
AA1 AA2
VSS2
VDDIO33PCIX
AA3 AA4
CLK
AA5
N/C
AA6
AD[20] VDDIO5PCIX
AB6
AD[24]
AA7
AD[21]
AA8 AA9
GNT/
AB1 AB2
VSS2
VDDIO33PCIX
AB3
AD[26]
AB4
AD[25]
AB5
N/C
AB7 AB8
N/C
AB9
TRDY/
AB10 AB11 AB12 AB13
REQ/
AC1
AD[28]
AC2
AD[22]
AC3 AC4
VSS2
VDDIO33PCIX
AC5 AC6
VSS2 VDDIO5PCIX
AD6
FRAME/
AC7 AC8
N/C
AC9
N/C
AD[12]
AC10 AC11
N/C VDDIO33PCIX
AD11
AD[11]
AC12 AC13
N/C
AD[29]
AD1
VDDIO5PCIX
AD2
PLL_VSS
AD3
PLL_VDD
AD4
VDDIO33PCIX
AD5
N/C
AD7
C_BE[1]/
AD8 AD9
N/C
VSS2
AD10
VDDIO5PCIX
AD12 AD13
N/C VDDIO33PCIX
AE13
AD[31]
AE1
C_BE[3]/
AE2 AE3
IDSEL
AD[18]
AE4
DEVSEL/
AE5
C_BE[2]/
AE6
VDDIO33PCIX
AE7
VDDIO33PCIX
AE8 AE9
PAR
AD[14]
AE10 AE11
N/C
VDDIO33PCIX
AE12
AD[27]
AF2
N/C
AF3
AD[23]
AF4
AD[19]
AF5
AD[17]
AF6
STOP/
AF7
VSS2
AF8
VSS2 VDDIO5PCIX
AD[10]
AF9
C_BE[0]/
AF10
AD[7]
AF11
VSS2
AF12
VSS2
AF13
VSS2
SERR/
AD[16]
AD[15]
IRDY/
PERR/
AD[13]
AD[8]
AD[9]
AD[6]
AD[4]
24 of 30
DB08-000215-04
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Figure 4
A14 A15
LSISAS1064 472-Pin BGA Top View (Cont.)
A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
RX3-
B14
TX_VSS2
B15 B16
N/C
TXB_VSS2
B17
TXB_VDD2
B18 B19
TX1-
B20
TX1+
B21
N/C
RX_VDD1
B22 B23
TX0-
B24
TX0+
B25
VSS2
B26
VSS2
C14 C15
VSS2
C16
RX2+
RX_VSS2
C17
RXB_VSS2
C18 C19
VSS2
C20
VSS2
C21
RX1+
C22
N/C
C23
N/C
C24
RX0+
C25
RX0-
MAD[0]
C26
N/C
D14 D15
N/C
D16
RX2-
RXB_VDD2
D17
TX_VDD1
D18 D19
N/C
D20
N/C
D21
RX1-
TX_VDD0
D22
RX_VDD0
D23
MAD[4]
D24
MAD[3]
D25
MAD[10]
D26
N/C
E14 E15
N/C
E16
N/C
E17
VSS2
TX_VSS1
E18
TXB_VSS1
E19
TX_VSS0
E20
TXB_VSS0
E21 E22
N/C
MAD[11]
E23
MAD[7]
E24
MAD[8]
E25
MAD[6]
E26
RX_VDD2
N/C
N/C
N/C
TXB_VDD1
F18
RXB_VDD1
F19
RXB_VSS1
F20 F21
VSS2 ISTW_ DATA
G21
VDDIO33
F22 F23
VSS2
MAD[5]
F24
MAD[9]
F25
MOE[1]/
F26
RX_VSS1
TXB_VDD0
G19
RX_VSS0
G20
ISTW_CLK
G22
MAD[1]
G23
VDDIO33
G24 G25
VSS2
REFCLK_P
G26
RXB_VDD0
RXB_VSS0
H20
MADP[0]
H21 H22
N/C
MAD[2]
H23
VDDIO33
H24 H25
VSS2
NVSRAM_ CS/
H26
VSS2
MAD[12]
J21 J22
N/C
MAD[13]
J23
MAD[15]
J24
MWE[1]/
J25
FLASH_ CS/
J26
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N/C
REFCLK_N
K22 K23
N/C
PSBRAM_ CS/
K24
BWE[2]/
K25
MADP[1]
K26
N/C
L22
VDDIO33
L23
MAD[14]
L24 L25
N/C
TDIODE_N
L26
N/C
M14 M15 M22 M23
VSS2
VDDIO33
M24 M25
VSS2
MWE[0]/
M26
VSS2
N14 N15
VDD2
MOE[0]/
N22
TDIODE_P
N23
VDDIO33
N24 N25
VSS2
BWE[1]/
N26
VDD2
P14 P15
VSS2
BWE[0]/
P22 P23
N/C
P24
N/C
BWE[3]/
P25 P26
MCLK
VSS2
R14 R15
VDD2
R22
N/C
ADSC/
R23
VDDIO33
R24 R25
VSS2
MADP[2]
R26
VDD2
VSS2
MAD[29]
T22
MAD[21]
T23
VDDIO33
T24 T25
VSS2
MAD[19]
T26
MAD[23]
U22
VDDIO33
U23
MAD[18]
U24 U25
N/C
MAD[17]
U26
N/C
V21 V22 V23
VSS2
MAD[24]
V24
MAD[20]
V25 V26
ADV/
BZR_SET
W20 W21 W22
N/C
W23
N/C
MAD[27]
W24
MAD[26]
W25
MAD[16]
W26
AD[37]
Y19 Y20 Y21
N/C
Y22
N/C
MADP[3]
Y23
VDDIO33PCIX
Y24 Y25
VSS2
MAD[28]
Y26
VSS2
AA18 AA19
AD[41]
AA20 AA21
N/C VDDIO5PCIX
AB21
AD[36]
AA22
VDDIO5PCIX
AA23
VDDIO33PCIX
AA24
VSS2
AA25
MAD[22]
AA26
N/C
AB14 AB15 AB16 AB17 AB18
AD[49]
AB19
AD[46]
AB20
VSS2
AB22
AD[35]
AB23
BZVDD
AB24
MAD[30]
AB25
MAD[25]
AB26
VDDIO5PCIX
AC14 AC15
N/C
AC16
N/C
PAR64
AC17
VDDIO5PCIX
AC18
AD[53]
AC19
VDDIO5PCIX
AC20
AD[44]
AC21
VDDIO33PCIX
AC22
VDDIO33PCIX
AC23
AD[32]
AC24
AD[38]
AC25
MAD[31]
AC26
N/C
AD14 AD15
N/C VDDIO33PCIX
AE15
VSS2
AD16
VDDIO33PCIX
AD17 AD18
N/C
AD[61]
AD19
AD[45]
AD20 AD21
N/C VDDIO33PCIX
AE21
VSS2
AD22
AD[48]
AD23
AD[40]
AD24
AD[39]
AD25
AD[33]
AD26
AD[2]
AE14
VDDIO33PCIX
AE16
VDDIO5PCIX
AE17
REQ64/
AE18
C_BE[5]/
AE19
VDDIO33PCIX
AE20
AD[54]
AE22
AD[55]
AE23
AD[42]
AE24
AD[47]
AE25
AD[34]
AE26
N/C
AF14
VSS2
AF15
VSS2
AF16
AD[1]
AF17
ACK64/
AF18
C_BE[7]/
AF19
VSS2
AF20
VSS2
AF21
AD[58]
AF22
AD[59]
AF23
AD[51]
AF24
AD[50]
AF25
VSS2
AD[0]
AD[3]
AD[5]
C_BE[6]/
C_BE[4]/
AD[63]
AD[62]
AD[60]
AD[56]
AD[57]
AD[52]
AD[43]
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
25 of 30
Package Drawings
The LSISAS1064 is packaged in a 472-EPBGA-T package with a 27 mm x 27 mm footprint and 1.0 mm ball pitch. The package code is UO. The package drawing number is JZ02-000015-00. Figure 5 provides the package diagram for the LSISAS1064.
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26 of 30
DB08-000215-04
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Figure 5
472-Pin EPBGA-T (UO) Mechanical Drawing
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Important:
For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
27 of 30
Figure 5
472-Pin EPBGA-T (UO) Mechanical Drawing--Bottom View (Cont.)
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Important:
For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO.
28 of 30
DB08-000215-04
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
Figure 5
472-Pin EPBGA-T (UO) Mechanical Drawing--Bottom View (Cont.)
www..com
Important:
For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UO.
LSISAS1064 4-Port 3 Gbit/s Serial Attached SCSI Controller
DB08-000215-04 January 2005 - Version 2.0 Copyright (c) 2003, 2004, 2005 by LSI Logic Corporation. All rights reserved.
29 of 30
www..com
Headquarters
LSI Logic Corporation North American Headquarters Milpitas CA Tel: 408.433.8000
LSI Logic Europe Ltd European Headquarters Bracknell England Tel: 44.1344.413200 Fax: 44.1344.413254
LSI Logic K.K. Headquarters Tokyo Japan Tel: 81.3.5463.7821 Fax: 81.3.5463.7820
To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales offices, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/index.html.
ISO 9000 Certified
This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic, the LSI Logic logo design, Fusion-MPT, Gflx, GigaBlaze, Integrated Mirroring, Integrated RAID, and Integrated Striping are trademarks or registered trademarks of LSI Logic Corporation. ARM and ARM Multi-ICE are registered trademarks of ARM Ltd., used under license. CompactPCI is a registered trademark of the PCI Industrial Computer Manufacturers Group. Purchase of I2C components of LSI Logic Corporation, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C standard Specification as defined by Philips. All other brand and product names may be trademarks of their respective companies. LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties.
AP Printed in USA Doc. No. DB08-000215-04

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